.\" Copyright (c) 2017
.\"	Tom Jones <tj@enoti.me>  All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
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.Dd November 17, 2017
.Dt CHVGPIO 4
.Os
.Sh NAME
.Nm chvgpio
.Nd Intel Cherry View SoC GPIO controller
.Sh SYNOPSIS
.Cd "device gpio"
.Cd "device chvgpio"
.Sh DESCRIPTION
.Nm
supports the GPIO controller that can be found in Intel's Cherry View SoC
family.
.Pp
The Cherry View SoC has 5 banks of GPIO pins, NORTH, EAST, SOUTHEAST, SOUTHWEST
and VIRTUAL.
All but VIRTUAL are exposed to userland as
.Pa /dev/gpiocN ,
where N is 0-3.
Pins in each bank are pre-named to match names in the Intel® Atom™ Z8000
Processor Series Vol 2
.Sh SEE ALSO
.Xr gpio 3 ,
.Xr gpio 4 ,
.Xr gpioctl 8
.Rs
.%T Intel® Atom™ Z8000 Processor Series Vol 1
.Re
.Rs
.%T Intel® Atom™ Z8000 Processor Series Vol 2
.Re
.Sh HISTORY
The
.Nm
manual page first appeared in
.Fx 12 .
.Sh AUTHORS
This driver and man page were written by
.An Tom Jones Aq Mt tj@enoti.me .
